Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - MAX PLUS II

Search list

[Other] quartus2

Description: 您现在阅读的是 Quartus II 简介手册。 Altera® Quartus® II 设计软件是适合 单芯片可编程系统 (SOPC) 的最全面的设计环境。 如果您以前用过 MAX+PLUS® II 软件、其它设计软件或 ASIC 设计软件，并且准备改用 Quartus II 软件，或如果您对 Quartus II 软件有了一些了解但想进一步了解 它的功能，那么本手册非常适合您。 -You are now reading the Quartus II brochure. Altera ® Quartus ® II design software is suitable for single-chip programmable system (SOPC) the most comprehensive design environment. If you have previously used the MAX+ PLUS ® II software, ASIC design software or other design software, and is prepared to use Quartus II software, or if you have some idea of Quartus II software, but would like to learn more about its capabilities, then this manual is for you.
Platform: | Size: 3096576 | Author: 倪萍波 | Hits:

[Other] MaxPlusChineseTuturial

Description: max-plus 简单用户使用入门指南。包括软件安装，图形设计，编译，定时分析，器件编程等详细介绍。-Max+Plus II Chinese Tuturial
Platform: | Size: 413696 | Author: 文静 | Hits:

[Other Embeded program] AutomobiletaillightcircuitPLDrealization

Description: 这个话题主要基于可编程逻辑器件,用硬件描述语言(VHDL)硬件描述语言(VHDL),采用“自顶向下”的设计方法,写一汽车尾灯控制器芯片,并且使用“最大加二世的软件模拟的结果。-This topic is mainly based on programmable logic devices, use VHDL VHDL, adopting "top-down" design methods, write an automobile tail light controller chip, and use the Max Plus II software simulation results.
Platform: | Size: 874496 | Author: 吴丹 | Hits:

[VHDL-FPGA-Verilog] pc8_1

Description: MAX+PLUS II BASELINE Version 8.1 Software
Platform: | Size: 39269376 | Author: hcet | Hits:

[VHDL-FPGA-Verilog] VHDL5.2

Description: In this report the design, implementation and testing of a Combination State Lock Machine from the given information, all of the design steps will be carried out using altera Max Plus II software package.
Platform: | Size: 244736 | Author: zyad | Hits:

[VHDL-FPGA-Verilog] electronic-lock-and-VHDL-design

Description: 基于Max+Plus II和VHDL的电子密码锁设计-Based on Max+ Plus II electronic lock and VHDL design
Platform: | Size: 1024 | Author: 于春秀 | Hits:

[VHDL-FPGA-Verilog] Four-adder-of-subtracter

Description: 在max+plus II 的环境下设计4位全加器数字电路 使用vhdl语言，进行设计数字电路的RTL级电路 -Four full adder digital circuit design environment, max+ plus II RTL-level circuit, digital circuit design using vhdl language
Platform: | Size: 567296 | Author: 东方不败 | Hits:

[VHDL-FPGA-Verilog] vhdl-hardware-implementation

Description: 本书主要介绍了VHDL的基础知识和硬件实现技术。全书由三部分组成：第一部分介绍了VHDL语法和程序结构，第二部分介绍MAx+plus II仿真软件的使用方法和数字逻辑电路的VHDL程序设计实例，第三部分介绍了硬件实现和硬件设计技巧。读者可以通过本书初步学会VHDL的使用，并对硬件实现中的关键技术问题有所理解和认识，快速掌握VHDL及其应用，并初步掌握硬件实现的关键技术。-This book introduces the VHDL basics and hardware implementation technology. The book consists of three parts: the first part of VHDL syntax and program structure, the second section describes the MAx+ plus II simulation software use and digital logic circuit design example of the VHDL program, the third section describes the hardware implementation and hardware design skills . Readers through the book preliminary learn the use of VHDL, and hardware implementation of the key technical issues have understanding and knowledge, to grasp the VHDL and its application, and preliminary master the key technology of the hardware implementation.
Platform: | Size: 15122432 | Author: 东方不败 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA交通灯说明： 1. 本程序使用VHDL加原理图方式设计而成。 2. 实验时，使用Quartus II软件完成了工程管理与下载验证，使用max+plus II软件进行了功能仿真。 3. 由于实验当时对原理图文件缺乏足够的认识，导致原原理图以及仿真输出文件已经丢失。现在的工程 RTL视图以及仿真输出波形均是在Quartus II软件下得到的。-FPGA traffic lights shows:1procedures for the use of the VHDL schematic design and.In 2 experiments, using Quartus II software to complete the project management and download validation, use max+plus II software to carry out the function simulation.The 3experiment was due to schematic document lacks enough understanding, resulting in the original diagram and simulation output file is missing. Now the engineering RTL view as well as the simulation output waveform are in Quartus II software under.
Platform: | Size: 455680 | Author: WangQunfeng | Hits:

[VHDL-FPGA-Verilog] eda6

Description: 以Altera公司的MAX+plus II为工具软件，采用Verilog HDL文本输入设计法设计8位二进制加减计数器，生成元件符号-Altera s MAX+plus II tools software, using Verilog HDL text input method to design8 binary addition and subtraction counter, generating element symbol
Platform: | Size: 34816 | Author: 王宇 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，在Altera公司的EDA软件平台MAX+PLUSⅡ环境下通过了编译、仿真，并下载到CPLD器件上进行编程制作，实现了交通灯系统的控制过程。-And select and use Description Language applying broader VHDL hardware circuit at present in capital being designed, the hardware circuit coming true to systematic controller of crossing traffic light describes that, have passed compiling , have simulated under EDA of Altera company software platform MAX+ PLUS II environment, download the control procedure having made , realizing traffic light systematically to the programming being in progress on CPLD component.
Platform: | Size: 266240 | Author: 陈金峰 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog 中文教學 1.簡介 2. Verilog 的模型 3. Verilog 的架構 4. MAX+plus II 的 環境 5. 基本資料型態 6. 輸出入埠的宣告 7. 邏輯閘階層模型的敘述 8. 資料流模型的敘述 9. 行為模型的敘述 10. 編譯命令 11. 循序邏輯電路範例
Platform: | Size: 600064 | Author: bill | Hits:

[Windows Develop] MaxPlusII

Description: Max+Plus II 简易用户使用入门指南,适合于初学者。-Max+Plus II
Platform: | Size: 236544 | Author: 痴心绝对 | Hits:

[Other] stopwatch

Description: 24小时计时表和计数译码显示电路的编程，显示秒、分、小时， MAX+plus II 仿真。-24 hours stopwatch and count decoding display circuit programming, display seconds, points, hours, MAX+ plus II simulation.
Platform: | Size: 218112 | Author: 宋辉 | Hits:

[VHDL-FPGA-Verilog] Multi-function-waveform-generator

Description: 本系统应用VHDL语言及MAX+PLUS II仿真软件利用自顶向下的设计思想进行设计，结合示波器加以完成一个可应用于数字系统开发或实验时做输入脉冲信号或基准脉冲信号用的信号发生器，它具结构紧凑，性能稳定，设计结构灵活，方便进行多功能组合的特点，经济实用，成本低廉。具有产生四种基本波形脉冲信号（方波、三角波、锯齿波和正弦波），且脉冲信号输出幅度及输出频率可调，对于方波信号，还可以实现占空比可调。通过软件仿真和硬件测试都得到了预期的结果。-The system using VHDL language and MAX+ PLUS II simulation software using a top-down design ideas to design a combined oscilloscope be completed to do the input pulse signal or reference pulse signal with the signal generator used in digital system development or experimentalwith compact structure, stable performance, flexible structure design, convenient multifunction portfolio characteristics, economical and practical, low cost. Has four basic waveform pulse signal (square wave, triangle wave, sawtooth and sine wave), and the amplitude of the pulse signal output and the output frequency is adjustable, adjustable duty cycle square wave signal can also be achieved. Expected results through software simulation and hardware testing.
Platform: | Size: 1485824 | Author: xinxing | Hits:

[VHDL-FPGA-Verilog] 24seconds

Description: 24秒倒计时的vhdl程序，采用Max plus -24 seconds countdown vhdl procedures, using Max plus II
Platform: | Size: 406528 | Author: wjk | Hits:

[VHDL-FPGA-Verilog] frqcounter

Description: 频率计vhdl代码，采用max plus -Frequency counter vhdl code using max plus II
Platform: | Size: 81920 | Author: wjk | Hits:

[Other] 6renqiangdaqi

Description: 包括做实验的所有文件打包给大家啦，MAX+plus II设计电路图，gdf文件，mod文件，报告书，一切齐全啦，当时被评为优秀成绩的，特别推荐给大家，电路绝对优秀，直接上机操作，导入电路图即可验证演示。-Including all the files packaged experiment to you friends, MAX+ plus II design schematics, gdf files, mod files, reports, everything is complete you, then was named outstanding achievements, particularly recommended for everyone, circuit absolutely outstanding, directly on the machine operation, import circuit can verify demonstration.
Platform: | Size: 357376 | Author: zxy | Hits:

[Other] 16lucaidengxunhuandianlu

Description: 16路彩灯循环控制电路设计 报告书 优秀成绩.包括做实验的所有文件打包给大家啦，MAX+plus II设计电路图，gdf文件，mod文件，报告书，一切齐全啦，当时被评为优秀成绩的，特别推荐给大家，电路绝对优秀，直接上机操作，导入电路图即可验证演示。-Including all the files packaged experiment to you friends, MAX+ plus II design schematics, gdf files, mod files, reports, everything is complete you, then was named outstanding achievements, particularly recommended for everyone, circuit absolutely outstanding, directly on the machine operation, import circuit can verify demonstration.
Platform: | Size: 576512 | Author: zxy | Hits:

[Other] dianzimimasuo

Description: 南京工程学院 数电课程设计 电子密码锁 所有实验文件打包.包括做实验的所有文件打包给大家啦，MAX+plus II设计电路图，gdf文件，mod文件，报告书，一切齐全啦，当时被评为优秀成绩的，特别推荐给大家，电路绝对优秀，直接上机操作，导入电路图即可验证演示。-Number of Nanjing Institute of Electrical curriculum design electronic locks files packaged all experiments, including experiments, all files are packaged to give you friends, MAX+ plus II design schematics, gdf files, mod files, reports, everything is complete you, then was named excellent results, especially recommended for everyone, circuit absolutely outstanding, directly on the machine operation, import circuit can verify demonstration.
Platform: | Size: 54272 | Author: zxy | Hits:
« 1 2 3 45 »

CodeBus www.codebus.net